1. Field of the Invention
The present invention relates to a semiconductor device having a crack resistant contact hole pattern, and to a method for fabricating a semiconductor device having a crack resistant contact hole.
2. Discussion of the Related Art
In general, performing process steps on a wafer requires a high degree of accuracy. In addition, it is necessary to remove either a wafer having a low yield or a wafer which does not have a standard size. In this regard, it is necessary to test and evaluate the wafer after respective process steps.
For such test and evaluation, a test pattern is formed in a scribe lane surrounding chips on the wafer to evaluate the wafer after completing respective process steps. Alternatively, a test wafer such as a void wafer or a wafer scrap included in a wafer holder may be used to evaluate main process steps.
It is important to align the wafer to associate a previous process step and the next process step. If the next process step is performed when the wafer is not adequately aligned, a low quality wafer with a reduced yield will likely be the result.
For this reason, study continues to improve alignment accuracy between a previous process step and the next process step by forming a pattern and a photo key, for monitoring the process steps, in the scribe lane surrounding the chips on the wafer.
The pattern and the photo key for monitoring the process steps in one frame of a conventional semiconductor device will be described with reference to the accompanying drawings.
FIG. 1 is a plane view of one frame in a conventional wafer. Referring to FIG. 1, a wafer 1 includes chips 2 for forming semiconductor devices and a scribe lane 3. The scribe lane 3 surrounds the chips 2 and allows the chips 2 to be separated from one another. One chip 2 and a scribe lane 3 surrounding the chip 2 are included in one frame. The wafer 1 further includes a test device such as an engineering test die for controlling quality during the sequence of process steps, an edge die formed at edge portions of the wafer 1, and wafer flats for indicating the crystal structure of the wafer. The edge die is also called an unfinished die. In addition, the scribe lane 3 surrounding the chips 2 includes a test pattern 4 and a variety of photo keys 5 for monitoring the process steps. The test pattern 4 evaluates whether the previous process step has been successfully performed. The photo keys 5 are used to monitor process steps such as aligning the wafer 1. Although the shape of the photo keys 5 depends on the equipment forming the photo keys 5, they are generally formed in a rectangular shape.
A method for forming a contact hole serving as a photo key, used to monitor the process steps, in the scribe lane of one frame will be described below with reference to the accompanying drawings.
FIG. 2 is a plane view of a contact hole in a scribe lane in one frame of a conventional semiconductor device. FIG. 3a to FIG. 3c are sectional views of the conventional process steps taken along line III--III of FIG. 2.
Referring to FIG. 2, a contact hole 14 has a lower layer pattern 11 formed on a predetermined region of a scribe lane region of a semiconductor substrate 10. An insulating film 13 is formed over the lower layer pattern 11 to protect, insulate and planarize the lower layer pattern 11. The contact hole 14 is formed by selectively removing some portion of the insulating film 13. The contact hole 14 has a rectangular shape.
As shown in FIG. 3a, a lower layer is formed on a semiconductor substrate 10 in which a chip region (not shown) and a scribe lane region are defined. The lower layer is selectively patterned by photolithography and etching processes to form a lower layer pattern 11 on the semiconductor substrate 10. The lower layer pattern 11 is formed having desired dimensions in the scribe lane region on the semiconductor substrate 10, and is formed with dimensions suitable for monitoring the process steps.
As shown in FIG. 3b, a first insulating film 12 and a second insulating film 13 are sequentially formed over the entire surface of the semiconductor 10 including the lower layer pattern 11. The first insulating film 12 insulates or protects the lower layer pattern 11. The first insulating film 12 also includes an oxide film or a nitride film. The second insulating film 13 is formed of an inter layer dielectric (ILD) layer including borophosphosilicate glass (BPSG).
As shown in FIG. 3c, the first and second insulating films 12 and 13 are selectively patterned to form the contact hole 14 for monitoring the process steps. The contact hole 14 is a photo key.
After the second insulating film 13 is formed, the surface of the semiconductor substrate 10 is heat treated to improve planarization.
In the conventional method for forming a contact hole in a semiconductor device, the ILD layer including the BPSG is formed over the entire surfaces of the semiconductor substrate having the chip region and the scribe lane region, and is selectively etched to form the contact hole. The chip region is heat treated to improve planarization. When such a large sized contact hole is formed as the photo key for monitoring the process steps, cracks irregularly occur due to tensile stress in the contact hole and compressive stress between the lower layer pattern 11 and the ILD layer 13. In particular, corner portions of the rectangular shaped contact hole 14 suffer tensile stress which causes the cracks. It is thus difficult to form a reliable contact hole for monitoring the process steps. As a result, the yield of the semiconductor device and its reliability are reduced.